The inventive concept relates to semiconductor devices, and more particularly, to semiconductor devices that perform one or more post package repair (PPR) operation(s).
Semiconductor memory devices usually include one or more memory cell arrays (e.g., two dimensional and/or three dimensional) including memory cells arranged in a matrix of rows and columns. Memory devices often include so-called “redundancy memory cells” that may be used to functionally replace bad memory cell(s) identified among memory cells of a memory cell array. It is common to replace a row of memory cells containing one or more bad memory cells with a row of redundancy memory cells, “redundancy row”. A collection of steps required to replace a row of memory cells with a corresponding redundancy row may be termed a “repair operation”. In this context, a PPR operation refers to a repair operation that is performed after a memory device has been packaged.
As integration density of contemporary memory devices increases and semiconductor manufacturing processes become ever more fine, single memory cell failures have increased. In a PPR operation, a bad row having as few as a single bit failure may be replaced by a redundancy row. However, since the memory cells connected to the redundancy row will store unknown data, it is possible that the blind replacement of a bad row with a redundancy row might introduce additional bits errors into the data stored (or attempted to be stored) in the bad row.